| PREFACE PART I OVERVIEW CHAPTER 1 Introduction 1.1 Organization and Architecture 1.2 Structure and Function 1.3 Outline of the Book CHAPTER 2 Computer Evolution and Performance 2.1 A Brie History of Computers 2.2 Designing for Performance 2.3 Pentium and PowerPC Evolution 2.4 Recommended Reading 2.5 Problems PART II THE COMPUTER SYSTEM CHAPTER 3 System Buses 3.1 Computer Components 3.2 Computer Function 3.3 Interconnection Structures 3.4 Bus Interconnection 3.5 PCI 3.6 Futurebus+ 3.7 Recommended Reading 3.8 Problems APPENDIX3A Timing Diagrams CHAPTER 4 Internal Memory 4.1 Computer Memory System Overview 4.2 Semiconductor Main Memory 4.3 Cache Memory 4.4 Advanced DRAM Organization 4.5 Recommended Reading 4.6 Problems Appendix 4A Performance Characteristics of Two-Level Memories CHAPTER 5 External Memory 5.1 Magnetic Disk 5.2 RAID 5.3 Optical Memory 5.4 Magnetic Tape 5.5 Recommended Reading 5.6 Problems CHAPTER 6 Input/Output 6.1 External Devices 6.2 I/O Modules 6.3 Programmed I/O 6.4 Interrupt-Driven I/O 6.5 Direct Memory Access 6.6 I/O Channels and Processors 6.7 The External Interface 6.8 Recommended Reading 6.9 Problems CHAPTER 7 Operating System Support 7.1 Operation System Overview 7.2 Scheduling 7.3 Memory Management 7.4 Recommended Reading 7.5 Problems PART III THE CENTRAL PROCESSING UNIT CHAPTER 8 Computer Arithmetic 8.1 The Arithmetic and Logic Unit(ALU) 8.2 Integer Representation 8.3 Integer Arithmetic 8.4 Floating-Point Representation 8.5 Floating-Point Arithmetic 8.6 Recommended Reading 8.7 Problems APPENDIX 8A Number Systems CHAPTER 9 Instruction Sets:Characteristics and Functions 9.1 Machine Instruction Characteristics 9.2 Types of Operands 9.3 Types of Operations 9.4 Assembly Language 9.5 Recommended Reading 9.6 Problems APPENDIX9A Stacks APPENDIX9B Little-,Big-,and Big-Endian CHAPTER 10 Instruction Sets:Addressing Modes and Formats 10.1 Addressing 10.2 Instruction-Formats 10.3 Recommended Reading 10.4 Problems CHAPTER 11 CPU Structure and Function 11.1 Processor Organization 11.2 Register Organization 11.3 The Instruction Cycle 11.4 Instruction Pipelining 11.5 The Pentium Processor 11.6 The PowerPC Processor 11.7 Recommended Reading 11.8 Problems CHAPTER 12 Reduced Instruction Set Computers(RISCs) 12.1 Instruction Execution Characteristics 12.2 The Use of a Large Register File 12.3 Compiler-Based Register Optimization 12.4 Reduced Instruction Set Architecture 12.5 RISC Pipelining 12.6 Motorola 88510 12.7 MIPS R4650 12.8 The RISC versus CLSC Controversy 12.9 Recommended Reading 12.10 Problems CHAPTER 13 Superscalar Processors 13.1 Overview 13.2 Design Lssues 13.3 PowerPC 13.4 Pentium 13.5 Recommended Reading 13.6 Problems PART IV THE CONTROL UNIT CHAPTER 14 Control Unit Operation 14.1 Micro-operations 14.2 Control of the CPU 14.3 Hardwired Implementation 14.4 Recommended Reading 14.5 Problems CHAPTER 15 Microprogrammed Control 15.1 Basic Concepts 15.2 Microinstruction Sequencing 15.3 Microinstruction Execution 15.4 TI8800 15.5 Applications of Microprogramming 15.6 Recommended Reading 15.7 Problems PART V PARALLEL ORGANIZATION CHAPTER 16 Parallel Processing 16.1 Multiprocessing 16.2 Cache Coherence and the MESI Protocol 16.3 Vector Computation 16.4 Parallel Processors 16.5 Recommended Reading 16.6 Problems APPENDIX Digital Logic A.1 Boolean Algebra A.2 Gates 608 A.3 Combination Circuits A.4 Sequential Circuits A.5 Problems Glossary References Index |
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