数字逻辑基础与Verilog设计（英文影印版）

.chapter 3
implementation technology
3.1 transistor switches
3.2 nmos logic gates
3.3 cmos logic gates
3.4 negative logic system
3.5 standard chips
3.6 programmable logic devices
3.7 custom chips, standard cells, and gate arrays
3.8 practical aspects
3.9 transmission gates
3.10 implementation details for splds, cplds,and fpgas
3.11 concluding remarks
chapter 4
optimized implementation of logic functions
4.1 karnaugh map
4.2 strategy for minimization
4.3 minimization of product-of-sums forms
4.4 incompletely specified functions
4.5 multiple-output circuits
4.6 multilevel synthesis
4.7 analysis of multilevel circuits
4.8 cubical representation
4.9 a tabular method for minimization
4.10 a cubical technique for minimization
4.11 practical considerations
4.12 cad tools
4.13 concluding remarks
chapter 5
number representation and arithmetic circuits
5.1 positional number representation
5.2 addition of unsigned numbers
5.3 signed numbers
5.4 fast adders
5.5 design of arithmetic circuits using cad tools
5.6 multiplication
5.7 other number representations
5.8 ascii character code
chapter 6
combinational-circuit building blocks
6.1 multiplexers
6.2 decoders
6.3 encoders
6.4 code converters
6.5 arithmetic comparison circuits
6.6 verilog for combinational circuits
6.7 concluding remarks
chapter 7
flip-flops, registers,counters, ano a simple processor
7.1 basic latch
7.2 gated sr latch
7.3 gated d latch
7.4 master-slave and edge-triggered d hip-flops
7.5 t hip-flop
7.6 jk flip-hop
7.7 summary of terminology
7.8 registers
7.9 counters
7.10 reset synchronization
7.11 other types of counters
7.12 using storage elements with cad tools
7.13 using registers and counters with cad tools
7.14 design examples
7.15 concluding remarks
chapter 8
synchronous sequential circuits
8.1 basic design steps
8.2 state-assignment problem
8.3 mealy state model
8.4 design of finite state machines using cad
tools
8.5 serialadder example
8.6 state minimization
8.7 design of a counter using the sequential circuit approach..
8.8 fsm as an arbiter circuit
8.9 analysis of synchronous sequential circuits
8.10 algorithmic state machine (asm) charts
8.11 formal model for sequential cimuits
8.12 concluding remarks chapter 9
asynchronous sequential circuits
9.1 asynchronous behavior
9.2 analysis of asynchronous circuits
9.3 synthesis of asynchronous circuits
9.4 state reduction
9.5 state assignment
9.6 hazards
9.7 a complete design example
9.8 concluding remarks
chapter 10
digital system design
10.1 building block circuits
10.2 design examples
10.3 clock synchronization
10.4 concluding remarks
chapter 11
testing of logic circuits
11.1 fault model
11.2 complexity of a test set
11.3 path sensitizing
11.4 circuits with tree structure
11.5 random tests
11.6 testing of sequential circuits
11.7 built-in self-test
11.8 printed circuit boards
11.9 concluding remarks
appendix a
verilog reference
a.i documentation in vefilog code
a.2 white space
a.3 signals in vefilog code
a.4 identifier names
a.5 signal values, numbers, and parameters
a.6 net and variable types
a.7 operators
a.8 verilog module
a.9 gate lnstantiations
a.10 concurrent statements
a.11 procedural statements
a.12 using subcircuits
a.13 functions and tasks
a.14 sequential circuits
a.15 guidelines,for writing verilog code
a.16 max+plusli verilog support
a.17 concluding remarks
appendix b
tutorial 1
b.1 introduction
b.2 design entry using schematic capture
b.3 design entry using verilog
b.4 design entry using truth tables
b.5 mixing design-entry methods
appendix c
tutorial 2
c.1 implementing a circuit
c.2 implementing a circuit in a flex 10k fpga
c.3 downloading a circuit into a device
c.4 making pin assignments
c.5 concluding remarks
appendix d
tutorial 3
d.i design using verilog code
d.2 using an lpm module
d.3 design of a sequential circuit
d.4 design of a finite state machine
d.5 concluding remarks
appendix e
commercial devices
e.1 simple plds
e.2 complex plds
e.3 field-programmable gate arrays
e.4 transistor-transistor logic
index...