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| 《国外电子与通信教材系列·数字集成电路：电路、系统与设计（第2版）（英文版）》特点：只关注深亚微米CMOS器件。开发了一个用于手工分析的称为“通用MOS模型”的晶体管简单模型，并在全书中采用。设计举例从实际出发，强调数字集成电路的设计。突出了设计中的难点和设计指导。所有例子和思考题都采用0.25微米CMOS工艺。“设计方法插入说明”分散地穿插在书中，强调了设计方法学和设计工具在今天的设计过程中的重要性。每章末尾的综述探讨了未来的技术发展趋势。 自本书第一版于1996年出版以来，CMOS制造工艺继续以惊人的速度向前推进，工艺特征尺寸越来越小，而电路也变得越来越复杂，这对设计者的设计技术提出了新的挑战。器件在进入深亚微米范围后有了很大的不同，从而带来了许多影响数字集成电路的成本、性能、功耗和可靠性的新问题。本书第二版反映了进入深亚微米范围后所引起的数字集成电路领域的深刻变化和新进展，特别是深亚微米晶体管效应、互连、信号完整性、高性能与低功耗设计、时序及时钟分布等，起着越来越重要的作用。与第一版相比，这个版本更全面集中地介绍了CMOS集成电路。 这个网站是个动态的指南。通过网站提供指导材料，更便于对这些材料随时进行扩充。网站包括了本书的完整PPT文件，覆盖了书中全部内容、修订、勘误、设计课题以及详尽的教师授课用教辅资料。特别需要指出的是，本书所有习题已放在网站上（书中不含习题）。 |
| Part 1 The Fabrics Chapter 1 Introduction 1.1 A Historical Perspective 1.2 Issues in Digital Integrated Circuit Design 1.3 Quality Metrics of a Digital Design 1.3.1 Cost of an Integrated Circuit 1.3.2 Functionality and Robustness 1.3.3 Performance 1.3.4 Power and Energy Consumption 1.4 Summary 1.5 To Probe Further Reference Books References Chapter2 The Manufacturing Process 2.1 Introduction 2.2 Manufacturing CMOS Integrated Circuits 2.2.1 The Silicon Wafer 2.2.2 Photolithography 2.2.3 Some Recuning Process Steps 2.2.4 Simplified CMOS Process Flow 2.3 Design Rules-The Contract between Designer and Process Engineer 2.4 Packaging Integrated Circuits 2.4.1 Package Materials 2.4.2 Interconnect Levels 2.4.3 Thermal Considerations in Packaging 2.5 Perspective-Trends in Process Technology 2.5.1 Short-Term Developments 2.5.2 In the Longer Term 2.6 Summary 2.7 To Probe Further References Design Methodology Insert A lC LAYOUT A.l To Probe Further References Chapter3 The Devices 3.1 Introduction 3.2 The Diode 3.2.1 A First Glance at the Diode-The Depletion Region 3.2.2 Static Behavior 3.2.3 Dynamic， or Transient， Behavior 3.2.4 The Actual Diode-Secondary Effects 3.2.5 The SPICE Diode Model 3.3 The MOS（FET） Transistor 3.3.1 A First Glance at the Device 3.3.2 The MOS Transistor under Static Conditions 3.3.3 The ActuaI MOS Transistor-Some Secondary Effects 3.3.4 SPICE Models for the MOS Transistor 3.4 A Word on Process Variations 3.5 Perspective-Technology Scaling 3.6 Summary 3.7 To Probe Further References Design Methodology Insert B Circuit Simulation References Chapter 4 The Wire 4.1 Introduction 4.2 A First Glance 4.3 Interconnect Parameters-Capacitance， Resistance， and Inductance 4.3.1 Capacitance 4.3.2 Resistance 4.3.3 Inductance 4.4 Electrical Wire Models 4.4.1 The Ideal Wire 4.4.2 The Lumped Model 4.4.3 The Lumped RC Model 4.4.4 The Distributed rc Line 4.4.5 The Transmission Line …… Part 2 A Circuit Perspective Charter 5 The CMOS Inverter Chapter 6 Designing Combinational Logic Gates in CMOS Design Methodology Insert C How to Simulate Complex Logic Circuits Design Methodology Insert D Layout Techniques for Complex Gates Chapter 7 Designing Sequential Logic Circuits Part 3 A System Perspective Chapter 8 Implementation Strategies for Digital ICS Design Methodology Insert E Characterizing Logic and Sequential Cells Design Methodology Insert F Design Synthesis Chapter 9 Coping with Interconnect Chapter 10 Timing Issues in Digital Circuits Design Methodology Insert G Design Verification Chapter 11 Designing Arithmetic Building Blocks Chapter 12 Designing Memory and Array Structures Design Methodology Insert H Validation and Test of Manufactured Circuits Problem Solutions Index |
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