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(特价书)嵌入式微控制器与处理器设计(英文影印版)

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(特价书)嵌入式微控制器与处理器设计(英文影印版)

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作 者:(美)Charles Greg Osborn

出 版 社:机械工业出版社

出版时间:2010 年1月

I S B N:9787111292500

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内容简介

书籍
计算机书籍
  本书全面讲述了嵌入式微控制器的基础知识,重点在于让学生理解微控制器背后的基本概念,而不在于教授学生为某个具体器件编写软件。全书内容覆盖如下主要概念:数字信号处理、模糊逻辑和模数转换,以便学生更好地理解现实世界中的设计理念。本书强调微控制器处理器架构和技术的特点,使其更适合用作高校电子电气工程、计算机以及工程技术类相关专业的教材,还可用作专业嵌入式微控制器设计人员的参考书。
  本书特点
  阐述单个芯片和嵌入式微控制器处理器设计。
  讨论单个芯片微控制器设计流程和嵌入式处理器设计流程之间的差异。
  涵盖与现实世界设计有关的资料。
  介绍指令集体系结构(isa)的概念,让学生能够理解cisc和risc处理器系列的共性。
  讨论如何平衡处理器、存储器和软件三种技术,使学生更直接地思考半导体制造能力、分级存储结构和汇编器以及优化编译器。

作者简介

目录

chapter 1 embedded processors
1.0 microcontrollers 1
1.1 microcontroller markets 1
1.2 data path 2
1.3 commercial microcontrollers 2
1.4 soc core processors 2
1.5 relative soc unit volumes 3
1.6 very-large-scale integration (vlsi) chip design tools
1.7 intellectual property 4
1.8 instruction set architecture 6
1.9 return on investment 6
1.10 semiconductor technology developments 7
chapter 2 microcontroller architecture
2.0 computer on a chip 11
2.1 johnvon neumann 12
2.2 computer architectures 13
2.3 semiconductor technology 14
2.4 msi andlsi 16
2.5 electronic calculator 17
2.6 microprocessors 18
.2.7 microprocessor peripherals 20
2.8 i8051 microcontroller 21
2.9 risc introduction 22
2.10 fabless semiconductor company 24
2.11 embedded controller ip 26
2.12 application specific processors 27
2.13 summary 28
chapter 3 embedded microcontroller technology
3.0 integrated circuits 30
3.2 design abstraction 34
3.3 risc andc1sc 35
3.4 memory technology 38
3.5 instruction processing 44
3.6 program design 45
3.7 unified instruction set 47
3.8 risc instruction set architecture 48
3.9 processor logic 49
3.10 processor functional partitioning 51
3.11 five-stage pipeline 54
3.12 summary 56
chapter4 microcontroller functions
4.0 device functions 58
4. 1 transistor technology 59
4.2 memory technologies 61
4.3 hardware features 64
4.4 data input/output 68
4.5 synchronous serial communication 70
chapter 5 program design
5.0 program design 72
5.1 polling program 73
5.2 interrupts 76
5.3 real-time operating system 82
5.4 event-driven system 83
5.5 nucleus 83
5.6 system layering 84
5.7 risk 84
chapter 6 hardware/software debug
6.0 hardware/software debug 86
6.1 cots controller tools 87
6.2 embedded controller tools 88
6.3 first silicon 88
6.4 board-level probes 89
6.5 debug process steps 90
6.6 soc debug strategies 94
6.7 armsoc debug 96
6.8 mips soc debug 98
chapter 7 serial data communications
7.0 serial data communication 101
7.1 uart 101
7.2 spi- serial peripheral interface 105
7.3 i2c- inter-ic bus 108
7.4 can--controller area network 112
7.5 lin--local interconnect network 115
7.6 i2s--inter-lc sound 116
7.7 irda - infrared data association 118
7.8 usb- universal peripheral bus 119
7.9 bluetooth 122
chapter 8 analog to digital conversion
8.0 analog-to-digital conversion 127
8.1 analog-to-digital conversion overview 127
8.2 transducers 129
8.3 low-pass filter 130
8.4 sampling 131
8.5 shannon's sampling theorem 132
8.6 what is an adc? 133
8.7 analog-to-digital conversion algorithms 141
8.80versampling 150
chapter 9 digital signal processing
9.0 digital signal processing 153
9.1 whatisadsp? 154
9.2 dsp controller architectures 156
9.3 analog filters 159
9.4 digital filters 164
9.5 signal transformation 170
9.6 fast fourier transform 174
9.7 table addressing (76
chapter 10 fuzzy logic
10.o fuzzy logic 178
10.1 fuzzy logic method 180
10.2 fuzzy perception 180
10.3 fuzzy logic terminology 181
10.4 fuzzy expert system 182
10.5 linguistic variables 185
10.6 pldcontroller 189
10.7 fuzzy logic application 191
10.8 the rule matrix 192
10.9 defuzzification 198
10.10 tuning and system enhancement 199
chapter 11 8-bitmicrocontrollers
11.0 general-purpose microcontrollers 201
11.1 microchippic18f4520 202
11.2 zilog z8 encore! xp f0830 series 226
chapter 12 16-bitmicrocontroller
12.0 16-bit processor overview 250
12.1 freescale si2xd processor overview 250
12.2 texas instruments msp430tm family 288
chapter 13 intellectual property soc cores
13.0 soc overview 309
13.1 soc design challenges 310
13.2 the mips32 4k processor core family 318
13.3 overview of the arm1022e processor 336
chapter 14 tensilica configurable ip core
14.0 introduction: moore's law revisited 352
14.1 chip design process 354
14.2 tensilica xtensaarchitecture overview 372
14.3 principles of instruction set design 374
14.4 tensilica xtensa processor uniqueness 374
14.5 registers 375
14.6 instruction width 376
14.7 compound instructions 377
14.8 branches 378
14.9 instruction pipeline 380
14.10 limited instruction constant width 381
14.11 short instruction format 381
14.12 register windows 382
14.13 xtensa lx2 summary 383
chapter 15 digital signal processors
15.0 dsp overview 385
15.1 tms320c55x 385
15.2 analog devices adsp-bf535 blackfin processor 408
index

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