(特价书)基于FPGA的系统设计（英文影印版）

.2.3 transistor characteristics
2.4 cmos logic gates
2.4.1 static complementary gates
2.4.2 gate delay
2.4.3 power consumption
2.4.4 driving large loads
2.4.5 low-power gates
2.4.6 switch logic
2.5 wires
2.5.1 wire structures
2.5.2 wire parasitics
2.5.3 models for wires
2.5.4 delay through an rc transmission line
2.5.5 buffer insertion in rc transmission lines
2.5.6 crosstalk between rc wires
2.6 registers and ram
2.6.1 register structures
2.6.2 random-access memory
2.7 packages and pads
2.7.1 packages
2.7.2 pads
2.8 summary
2.9 problems
chapter 3 fpga fabrics
3.1 introduction
3.2 fpga architectures
3.3 sram-based fpgas
3.3.1 overview
3.3.2 logic elements
3.3.3 interconnection networks
3.3.4 configuration
3.4 permanently programmed fpgas
3.4.1 antifuses
3.4.2 flash configuration
3.4.3 logic blocks
3.4.4 interconnection networks
3.4.5 programming
3.5 chip i/o
3.6 circuit design of fpga fabrics
3.6.1 logic elements
3.6.2 interconnect
3.7 architecture of fpga fabrics
3.7.1 logic element parameters
3.7.2 interconnect architecture
3.7.3 pinout
3.8 summary
3.9 problems
chapter 4 combinational logic
4.1 introduction
4.2 the logic design process
4.3 hardware description languages
4.3.1 modeling with hdls
4.3.2 verilog
4.3.3 vhdl
4.4 combinational network delay
4.4.1 delay specifications
4.4.2 gate and wire delay
4.4.3 fanout
4.4.4 path delay
4.4.5 delay and physical design
4.5 power and energy optimization
4.5.1 glitching analysis and optimization
4.6 arithmetic logic
4.6.1 number representations
4.6.2 combinational shifters
4.6.3 adders
4.6.4 alus
4.6.5 multipliers
4.7 logic implementation for fpgas
4.7.1 syntax-directed translation
4.7.2 logic implementation by macro
4.7.3 logic synthesis
4.7.4 technology-independent logic optimization
4.7.5 technology-dependent logic optimizations
4.7.6 logic synthesis for fpgas
4.8 physical design for fpgas
4.8.1 placement
4.8.2 routing
4.9 the logic design process revisited
4.10 summary
4.11 problems
chapter 5 sequential machines
5.1 introduction
5.2 the sequential machine design process
5.3 sequential design styles
5.3.1 state transition and register-transfer models
5.3.2 finite-state machine theory
5.3.3 state assignment
5.3.4 verilog modeling styles
5.4 rules for clocking
5.4.1 flip-flops and latches
5.4.2 clocking disciplines
5.5 performance analysis
5.5.1 performance of flip-flop-based systems
5.5.2 performance of latch-based systems
5.5.3 clock skew
5.5.4 retiming
5.6 power optimization
5.7 summary
5.8 problems
chapter 6 architecture
6.1 introduction
6.2 behavioral design
6.2.1 data path-controller architectures
6.2.2 scheduling and allocation
6.2.3 power
6.2.4 pipelining
6.3 design methodologies
6.3.1 design processes
6.3.2 design standards
6.3.3 design verification
6.4 design example
6.4.1 digital signal processor
6.5 summary
6.6 problems
chapter 7 large-scale systems
7.1 introduction
7.2 busses
7.2.1 protocols and specifications
7.2.2 logic design for busses
7.2.3 microprocessor and system busses
7.3 platform fpgas
7.3.1 platform fpga architectures
7.3.2 serial i/o
7.3.3 memories
7.3.4 cpus and embedded multipliers
7.4 multi-fpga systems
7.4.1 constraints on multi-fpga systems
7.4.2 interconnecting multiple fpgas
7.4.3 multi-fpga partitioning
7.5 novel architectures
7.5.1 machines built from fpgas
7.5.2 altemative fpga fabrics
7.6 summary
7.7 problems
appendix a glossary
appendix b hardware description languages
b. 1 introduction
b.2 verilog
b.2.1 syntactic elements
b.2.2 data types and declarations
b.2.3 operators
b.2.4 statements
b.2.5 modules and program units
b.2.6 simulation control
b.3 vhdl
b.3.1 syntactic elements
b.3.2 data types and declarations
b.3.3 operators
b.3.4 sequential statements
b.3.5 structural statements
b.3.6 design units
b.3.7 processes
references
index