| contents foreword xv preface xvii 1 introduction 1．1 about digital design 1．2 analog versus digital 1．3 digital devices 1．4 electronic aspects of digital design 1．5 software aspects of digital design 1．6 integrated circuits 1．7 programmable logic devices 1．8 application-specific ics 1．9 printed－circuit boards 1．10 digital-design levels 1．11 the name of the game 1．12 going forward drill probbems 2 number systems and codes 2．1 positional number systems 2．2 octal and hexadcimal numbers . 2．3 general positional－number－system conversions 2．4 addition and subtraction of nondecimal numbers 2．5 representation of negative numbers 34 2．5．1 signed－magnitude representation 2. 5．2 complement number systems 2．5．3 radix－complement representation 2. 5. 4 two's－complement representation 2．5．5 diminished radix-complement representation 2．5．6 one's－complement representation 2．5．7 excess representations 2．6 two's－complement addition and subtaction 2．6．1 addition rules 2．6. 2 a graphical view 2．6．3 overflow 2．6．4 subtraction rules 2．6. 5 two's－complement and unsigned binary numbers 2．7 ones'－complement addition and subtraction 2. 8 binary multiplication 2. 9 binary division 2．10 binary codes for decimal numbers 2．11 gray code 2．12 character codes 2．13 codes for actions，conditions，and states 2．14 n-cubes and distance 2．15 codes for detecting and correcting errors 2．15. 1 error－detecting codes 2．15. 2 error－correcting and multiple－error－detecting codes 2. 15．3 hamming codes 2．15．4 crc codes 2．15．5 two-dimensional codes 2. 15. 6 checksum codes 2．15．7 m－cut-of-n codes 2．16 codes for serial data transmission and storage 2．16. 1 parallel and serial data 2．16. 2 serial line codes references drill problems exercises 3 digital circuits 3．1 logic signals and gates 3．2 logic families 3．3 cmos logic 3．3．1 cmos logic levels 3．3．2 mos transistors 3．3. 3 basic cmos inverter circuit 3. 3. 4 cmos nand and nor gates 3. 3. 5 fan－in 3. 3．6 noninverting gates 3. 3．7 cmos and－or-invert and or－and－invert gates 3. 4 electrical behavior of cmos circuits 3．4．1 overiew 3．4．2 data sheets and specifications 3．5 cmos steady-state electrical behavior 3．5．1 logic levels and noise mangins 3．5. 2 circuit behavior with resistive loads 3．5. 3 circuit behavior with nonideal inputs 3．5. 4 fanout 3．5. 5 effects of loading 3．5．6 unused inputs 3．5．7 current spikes and decoupling capacitors 3. 5．8 how to destroy a cmos device 3. 6 cmos dynamic electrical behavior 3．6．1 transition time 3. 6．2 propagation delay 3. 6．3 power consumption 3．7 other cmos input and output structures 3．7．1 transmission gates 3．7．2 schmitt－trigger inputs 3．7．3 three－state outputs 3．7．4 open－drain outputs 3．7．5 driving leds 3．7．6 multisource buses 3. 7．7 wired logic 3. 7. 8 pull-up resistors 3．8 cmos logic families 3．8. 1 hc and hct 3．8．2 vhc and vhct 3．8．3 hc，hct， vhc，and vhct electrical characte characteristics 3．8. 4 fct and fct－t 3．8．5 fct-t electrical characteristics 3. 9 bipolar logic 3. 9. 2 diodes 3．9．2 diode logic 3．9．3 bipolar junction transistors 3. 9. 4 transistor logic inverter 3．9．5 schottky transistors 3．10 transistor-transistor-logic 3．10．1 basic ttl nand gate 3．10．2 logic levels and noise maryins 3. 10. 3 fanout 3．10．4 unused inputs 3．10．5 additional ttl gate types 3．11 ttl families 3．11．1 early ttl families 3. 11. 2 schottky ttl families 3. 11. 3 characteristics of ttl families 3．11．4 a ttl data sheet 3．12 cmos/ttl interfacing 3．13 low－voltage cmos logic and interfacing 3．13．1 3.3－vlvttl and lvcmos logic 3．13. 2 5－v tolerant inputs 3．i3．3 5－v tolerant outputs 3．13. 3 ttl/lvttl interfacing summary 3．13．5 2．5－v and 1．8－vlogic 3．14 emitter-coupled logic 3．14．1 basic cml circuit 3. 14．2 ecl 10k/10h families 3. 14．3 ecl 100k family 3．14．4 positive ecl（pecl） references drill problems exercises 4 combinational logic design principles 4. 1 switching algebra 4．1．1 axioms 4．1．2 single－variable theorems 4．1．3 two-and three-variable theorems 4．1．4 n－variable theorems 4．1．5 duality 4．1．6 standard reprentations of logic functions 4．2 combinational－circuit analysis 4．3 combinational－circuit synthesis 4．3．1 cinuit descriptions and designs 4．3．2 circuit manipulations 4．3．3 combinational－circuit minimization 4．3．4 karnaugh maps 4．3．5 minimizing sums of products 4．3．6 simplifying products of sums 4．3．7 “don't－care”input combinations 4．3. 8 multiple_output minimization 4. 4 programmed minimization methods 4．4．1 representation of product terms 4．4．2 finding prime implicants by combining product terms 4．4．3 finding a minimal cover using a prime－implicant table 4．4．4 other minimization methods 4．5 timing hazards 4. 5. 1 static hazards 4．5．2 finding static hazards using maps 4．5. 3 dynamic hazards 4. 5．4 designing hazard－free circuits 4．6 the abel hardware description language 4．6．1 abel program structure 4．6．2 abel complier operation 4．6．3 when statements and equation blocks 4．6. 4 truth tables 4．6．5 ranges，sets，and relations 4．6．6 don’t－care inputs 4. 6. 7 test vectors 4．7 the vhdl hardware description language 4．7．1 design flow 4．7．2 program structure 4．7．3 types and constants 4．7．4 functions and procedures 4．7．5 libraries and packages 4．7．6 strucral design elements 4．7．7 dataflow design elements 4．7．8 behavioral design elements 4．7．9 the time dimension and simulation 4．7. 10 synthesis references drill problems exercises 5 combinational logic design practices 5．1 documentstion standards 5. 1. 1 block diagrams 5．1．2 gate symbols 5. 1. 3 signal names and active levels 5．1. 4 active levels for pins 5．1．5 bubble－to－bubble logic design 5．1．6 drawing layout 5．1．7 buses 5. 1．8 additional schematic information 5．2 circuit timing 5．2．1 timing diagrams 5．2．2 propogation delay 5．2. 3 timing specifications 5．2．4 timing analysis 5．2．5 timing analysis tools 5. 3 combinational plds 5．3．1 programmable logic arrays 5．3．2 programmable array logic devices 5. 3．3 generic array logic devices 5. 3．4 bipolar pld circuits 5．3．5 cmos pld circuits 5．3．6 device programming and testing 5．4 decoders 5．4．1 binary decoders 5．4．2 logic symbols for larger－scale elements 5．4．3 the 74x139 dual 2-to-4 decoder 5．4．4 the 74xi38 3－to-8 decoder 5. 4．5 cascading binary decoders 5．4．6 decoders in abel and plds 5．4．7 decoders in vhdl 5．4．8 seven－segment decoders 5．5 encoders 5．5．1 priority encoders 5. 5. 2 the 74x148 priority encoder 5．5. 3 encoders in abel and plds 5. 5. 4 encoders in vhdl 5. 6 three-state devices 5．6．1 three－state buffers 5．6．2 standard ssi and msi three-state buffers 5．6．3 three－state outputs in abel and plds 5．6. 4 three- state outputs in vhdl 5．7 multiplexers 5. 7．1 standard msi multiplexers 5．7. 2 expanding multiplexers 5. 7. 3 multiplexers,demultiplexers，and buses 5. 7. 4 multiplexers in abel and plds 5. 7. 5 multiplexers in vhdl 5．8 exclusive－or gates and party circuits 5. 8. 1 exclusive－or and exclusive－nor gates 5．8．2 parity circuits 5. 8．3 the 74x280 9－bit parity generator 5．8．4 parity-checking applications 5．8. 5 exclusive－or gates and parity circuits in abel and plds 5．8. 6 exclusive－or gates and parity circuits in vhdl 5. 9 comparators 5．9．1 comparator structure 5．9．2 lterative circuits 5. 9．3 an iierative comparator circuit 5．9．4 standard msi comparators 5. 9. 5 comparators in abel and plds 5．9．6 comparators in vhdl 5．10 adders, subtractors,and alus 5．10．1 half adders and full adders 5．10．2 ripple adders 5．10．3 subtractors 5. 10．4 carry lookahead adders 5. 10．5 msi adders 5．10. 6 msi arithmetic and logic units 5．10．7 group－carry lookahead 5．10. 8 adders in abel and plds 5. 10．9 adders in vhdl 5．11 combinational multipliers 5．11．1 combinational multiplier structures 5．11. 2 multiplication in abel and plds 5．11．3 multiplication in vhdl references drill problems exercises 6 combnational－circuit design examples 6．1 buiding－block design examples 6．1．1 barrel shifter 6．1．2 simple floating－point encoder 6．1. 3 dual-priority encoder 6. 1．4 cascadinmp comparators 6．1．5 mode－dependent comparator 6．2 design examples using abel and plds 6．2. 1 barrel shifter 6. 2．2 simple floating－point encoder 6．2．3 dual－priority encoder 6．2．4 cascading comparators 6．2．5 mode－dependent comparator 6．2．6 ones counter 6．2．7 tic－tac－toe 6．3 design examples using vhdl 6．3．1 barrel shifter 6．3. 2 simple floating－point encoder 6．3．3 dual-priority encoder 6．3．4 cascading comparators 6．3. 5 mode－dependent comparator 6. 3. 6 ones counter 6．3. 7 tic-tac-toe exercises 7 sequential logic design principles 7. 1 bistable elements 7. 1. 1 digilai analysis 7. 1. 2 analog analysis 7．1. 3 metastable behavior 7. 2 latches and flip－flops 7. 2. 1 s-rlatch 7．2. 2 s-rlatch 7．2．3 s-rlatch with enable 7. 2．4 d latch 7. 2. 5 edge－triggered d flip－flop 7. 2．6 edge－triggered d flip－flop with enable 7. 2．7 scan flip－flop 7. 2. 8 master／slave s－r flip－flop 7. 2. 9 master／slave j-k flip-flop 7. 2. 10 edge-triggered j-k flip-flop 7. 2. 11 t flip-flop 7. 3 clocked synchronous state－machine analysis 7. 3. 1 state－machine structure 7．3. 2 output logic 7．3．3 characteristic equations 7. 3. 4 analysis of state machines with d flip－flops 7．3. 5 analysis of state machines with j－k flip－flops 7．4 clocked synchronous state－machine design 7．4．1 state－table design example 7. 4．2 state minimization 7．4．3 state assignment 7．4．4 synthesis using d flip－flops 7．4．5 synthesis using j-k flip－flops 7．4．6 more design examples using d flip－flops 7．5 designing state machines using state diagrams 7．6 state－machine synthesis using transition lists 7．6．1 transition equations 7．6．2 excitation equations 7．6．3 variations on the scheme 7．6. 4 redlizing the state machine 7．7 another state－machine design example 7．7．1 the guessing game 7. 7．2 unused states 7. 7. 3 output－coded state assignment 7．7．4 “don't－care”state codings 7．8 decomposing state machines 7．9 feedback sequential circuits 7．9．1 analysis 7．9．2 analyzing circuits with multiple feedback loops 7. 9. 1 races 7. 9. 4 state tables and flow tables 7. 9．5 cmos d flip－flop analysis 7. 10 feedback sequential－circuit design 7. 10．1 latches 7.10. 2 designing fundamental－mode flow table 7. 10. 3 flow－table minimization 7．10. 4 race－free state assignment 7．10. 5 excitation equations 7. 10. 6 essential hazards 7. 10．7 summary 7．11 abel sequential－circuit design features 7．11. 1 registered outputs 7. 11. 2 state diagrams 7．11. 3 external state memory 7．11．4 specifying moore outputs 7. 11. 5 specifying mealy and pipelined outputs with with 7．11. 6 test vectors 7. 12 vhdl sequential-circuit design features 7．12. 1 feedback sequential circuits 7．12. 2 clocked circuits references drill problems exercises 8 sequential logic design practices 8. 1 sequential-circuit documentation standards 8．1．1 general requirements 8．1．2 logic symbols 8．1．3 state－machine descriptions 8．1．4 timing diagrams and specifications 8．2 latches and flip-flops 8. 2. 1 ssi latches and flip-flops 8. 2. 2 switch debouncing 8．2．3 the simplest switch debouncer 8．2．4 bus holder circuit 8．2. 5 multibit registers and latches 8．2．6 registers and latches in abel and plds 8．2．7 registers and latches in vhdl 8. 3 sequential plds 8．3．1 bipolar sequential plds 8. 3. 2 sequential gal devices 8．3．3 pld timing specifications 8．4 counters 8．4．1 ripple counters 8. 4. 2 synchronous counters 8．4. 3 msi counters and applications 8．4．4 decoding binary-counter states 8．4. 5 counters in abel and plds 8．4. 6 counters in vhdl 8. 5 shift registers 8．5．1 shift－register structure 8．5．2 msi shitt registers 8．5．3 the world's biggest shift－register application 8．5．4 serial/parallel conversion 8. 5．5 shift－register counters 8. 5. 6 ring counters 8．5. 7 johnson counters 8．5．8 linear feedback shift－register counters 8．5. 9 shift registers in abel and plds 8．5．10 shift registers in vhdl 8．6 iterative versus sequential circuits 8．7 synchronous design methodology 8．7．1 synchronous system structure 8．7．2 a synchronous system design example 8．8 impediments to synchronous design 8. 8. 1 clock skew 8. 8. 2 gating the clock 8．8．3 asynchronous inputs 8．9 synchronizer failure and metastability 8．9．1 synchronizer failure 8．9．2 metastability resolution time 8．9．3 reliable synchronizer design 8．9. 4 analysis of metastable timing 8．9．5 better synchronizers 8．9．6 other synchronizer designs 8．9．7 metastable－hardened flip－flops 8．9．8 synchronizing hig-speed data transfers references drill problems exercises 9 sequential－circuit design examples 9．1 design examples using abel and plds 9．1．1 timing and packaging of pld-based state machines 9．1．2 a few simple machines 9．1．3 t-bird tail lights 9．1．4 the guessing game 9．1．5 reinventing traffic-light controllers 9．2 design examples using vhdl 9．2．1 a few simple machines 9．2．2 t-bird tail lights 9．2．3 the guessing game 9．2．4 reinventing traffic-light controllers exercises 10 memory,cplds, and fpgas 10．1 read－only memory 10．1．1 using roms for “random” combinational logic functions 10．1．2 internal rom structure 10．1. 3 two－dimensional decoding 10．1．4 commercial rom types 10．1．5 rom control inputs and timing 10．1. 6 rom applications 10．2 read／write memory 10. 3 static ram 10. 3. 1 static-ram inputs and outputs 10. 3. 2 static－ram internal structure 10. 3．3 static－ram timing 10．3．4 standard static rams 10．3. 5 synchronous sram 10．4 dynamic ram 10．4．1 dynamic－ram structure 10．4．2 dynamic－ram timing 10．4．3 synchronous drams 10．5 complex programmable logic devices 10. 5．1 xilinx xc9500 cpld family 10. 5．2 function－biock architecture 10．5．3 input/output-biock architecture 10. 5．4 switch matrix 10．6 field-programmable gate arrays 10．6．1 xilinx xc4000 fpga family 10. 6. 2 configurable logic block 10．6. 3 input／outpot block 10. 6. 4 programmable interconnect references drill problems exercises 11 additional real-world topics 11．1 computer-aided design tools 11．1．1 hardware description languages 11．1．2 schematic capture 11．1．3 timing drawings and specifications 11. 1．4 circuit analysis and simulation 11．1．5 pcb layout 11．2 design for testability 11．2. 1 testing 11．2．2 bed－of-nails and in－circuit testing 11．2．3 scan methods 11．3 estimating digital system reliablity 11. 3．1 failure rates 11. 3. 2 reliability and mtbf 11．3. 3 system reliability 11．4 transmission lines，reflections,and termination 11．4．1 basic transmission－line theory 11. 4. 2 logic－signal interconnections as transmission lines 11. 4. 3 logic－signal terminations references index |
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