| preface to the third edition preface to the second edition preface 1 digital systems and vlsi 1.1 why design integrated circuits? 1.2 integrated circuit manufacturing 1.3 cmos technology 1.4 integrated circuit design techniques 1.5 a look into the future 1.6 summary 1.7 references 1.8 problems 2 transistors and layout 2.1 introduction 2.2 fabrication processes 2.3 transistors 2.4 wires and vias 2.5 design rules 2.6 layout design and tools 2.7 references .2.8 problems 3 logic gates 3.1 introduction 3.2 combinational logic functions 3.3 static complementary gates 3.4 switch logic 3.5 alternative gate circuits 3.6 low-power gates 3.7 delay through resistive interconnect 3.8 delay through inductive interconnect 3.9 references 3.10 problems 4 combinational logic networks 4.1 introduction 4.2 standard cell-based layout 4.3 simulation 4.4 combinational network delay 4.5 logic and interconnect design 4.6 pwer optimization 4.7 switch logic networks 4.8 combinational logic testing 4.9 references 4.10 problems 5 seqential machines 5.1 introduction 5.2 latches and flip-flops 5.3 sequential systems and clocking disciplines 5.4 sequential system design 5.5 power optimaization 5.6 design validation 5.7 sequential testing 5.8 references 5.9 problems 6 subsystem design 6.1 introduction 6.2 subsystem design principles 6.3 combinational shifers 6.4 adders 6.5 alus 6.6 multipliers 6.7 high-density memory 6.8 field-programmable gate arrays 6.9 programmable logic arrays 6.10 refernces 6.11 problems 7 floorplanning 7.1 introduction 7.2 floorplanning methods 7.3 off-chip connections 7.4 references 7.5 problems 8 architecture design 8.1 introduction 8.2 hardware description languages 8.3 register-transfer design 8.4 high-level synchesis 8.5 architectures for low power 8.6 systems-on-chips and embedded cpus 8.7 architecture testing 8.8 references 8.9 problems 9 chip design 9.1 introduction 9.2 design methodologies 9.3 kitchen timer chip 9.4 microprocessor data path 9.5 references 9.6 problems 10 cad systems and algorithms 10.1 introduction 10.2 cad systems 10.3 switch-level simulation 10.4 layout synthesis 10.5 layout analysis 10.6 timing analysis and optimization 10.7 logic synthesis 10.8 test generation 10.9 sequential machine optimizations 10.10 scheduling and binding 10.11 hardware/software co-design 10.12 references 10.13 problems a chip designer's lexicon b chip design projects b.1 class project ideas b.2 project proposal and specification b.3 design plan b.4 design checkpoints and specification c kitchen timer model c.1 hardware modeling in c index |
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