| 1 introduction. 1.1 cad tool flows 1.2 what this book is and isn't 1.3 bugs in the tools? 1.4 tool setup and execution scripts 1.5 typographical conventions 2 cadence dfii and icfb 2.1 cadence design framework 2.2 starting cadence 2.3 summary 3 composer schematic capture 3.1 starting cadence and making a new working library 3.2 creating a new cell 3.3 schematics that use transistors 3.4 printing schematics 3.5 variable, pin, and cell naming restrictions 3.6 summary 4 verilog simulation 4.1 verflog simulation of composer schematics 4.2 behavioral verilog code in composer .4.3 stand-alone verilog simulation 4.4 timing in verilog simulations 4.5 summary 5 virtuoso layout editor 5.1 an inverter schematic 5.2 layout for an inverter 5.3 printing layouts 5.4 design rule checking 5.5 generating an extracted view 5.6 layout versus schematic checking (lvs) 5.7 overall cell design flow (so far…) 5.8 summary 6 standard cell design template 6.1 standard cell geometry specification 6.2 standard cell i/o pin placement 6.3 standard cell transistor sizing 6.4 summary 7 spectre analog simulator 7.1 simulating a schematic (transient simulation) 7.2 simulation with the spectre analog environment 7.3 simulating with a config view 7.4 mixed analog/digital simulation 7.5 dc simulation 7.6 power measurements 7.7 summary 8 cell characterization 8.1 liberty file format 8.2 cell characterization with elc 8.3 cell characterization with spectre 8.4 converting liberty to synopsys database (db) format 8.5 summary 9 verilog synthesis.. 9.1 synopsys design compiler synthesis with dc_hell 9.2 cadence rtl compiler synthesis 9.3 importing structural verilog into cadence dfii 9.4 post-synthesis verilog simulation 9.5 summary 10 abstract generation 10.1 reading your library into abstract 10.2 finding pins in your cells 10.3 the extract step 10.4 the abstract step i0.5 lef file generation 10.6 modifying the lef file 10.7 summary 11 soc encounter place and route 11.1 encounter gui 11.2 design import with configuration files 11.3 soc encounter scripting 11.4 summary 12 chip assembly 12.1 module routing with ccar 12.2 core to pad frame routing with ccar 12.3 final gdsii generation 12.4 summary 13 design example 13.1 tiny mips 13.2 tiny mips: flat tool flow 13.3 tiny mips: hierarchical tool flow 13.4 summary a tool and setup scripts a.1 cadence tool installation a.2 cadence setup scripts a.3 shell scripts for cadence tools a.4 synopsys tool installation a.5 synopsys setup scripts a.6 shell scripts for synopsys tools a.7 summary b scripts to drive the tools b.1 tcl script basics b.2 cadence tool scripts b.3 synopsys tool scripts b.4 summary c technology and cell libraries c.1 ncsu cadence design kit cdk1.5 installation c.2 example standard cells c.3 summary bibliography index... |
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