Verilog HDL 高级数字设计（英文版）

.
2 review of combinational logic design

2.1 combinational logic and boolean algebra
2.1.1 asic library cells
2.1.2 boolean algebra
2.1.3 demorgan's laws
2.2 theorems for boolean algebraic minimization
2.3 representation of combinational logic
2.3.1 sum of products representation
2.3.2 product-of-sums representation
2.4 simplification of boolean expressions
2.4.1 simplification with exclusive-or
2.4.2 karnaugh maps(sop form)
2.4.3 karnaugh maps(pos form)
2.4.4 karnaugh maps and don't-cares
2.4.5 extended karnaugh maps
2.5 glitches and hazards
2.5.1 elimination of static hazards(sop form)
2.5.2 summary:elimination of static hazards in two-level circuits
2.5.3 static hazards in multilevel circuits
2.5.4 summary:elimination of hazards in multilevel circuits
2.5.5 dynamic hazards
2.6 building blocks for logic design
2.6.1 nadn-nor structures
2.6.2 multiplexers
2.6.3 demultiplexers
2.6.4 encoders
2.6.5 priority encoder
2.6.6 decoder
2.6.7 priority decoder
references
problems

3 fundamentals of sequential logic design

3.1 storage elements
3.1.1 latches
3.1.2 transparent latches
3.2 flip-flops
3.2.1 d-type flip-flop
3.2.2 master-slave flip-flop
3.2.3 j-k flip-flop
3.2.4 t flip-flop
3.3 busses and three-state devices
3.4 design of sequential machines
3.5 state-transition graphs
3.6 design example:bcd to excess-3 code converter
3.7 serial-line code converter for data transmission
3.7.1 a mealy-type fsm for serial line-code conversion
3.7.2 a moore-type fsm for serial line-code conversion
3.8 state reduction and equivalent states
references
problems

4 introduction to logic design with verilog

4.1 structural models of combinational logic
4.1.1 verilog primitives and design encapsulation
4.1.2 verilog structural models
4.1.3 module ports
4.1.4 some language rules
4.1.5 top-down design and nested modules
4.1.6 design hierarchy and source-code organization
4.1.7 vectors in verilog
4.1.8 structural connectivity
4.2 logic simulation,design verification,and test methodology
4.2.1 four-valued logic and signal resolution in verilog
4.2.2 test methodology
4.2.3 signal generators for testbenches
4.2.4 event-driven simulation
4.2.5 testbench template
4.2.6 sized numbers
4.3 propagation delay
4.3.1 inertial delay
4.3.2 transport delay
4.4 truth table models of combinational and sequential logic with verilog
references
problems

5 logic design with behavioral models of combinational and sequential logic

5.1 behavioral modeling
5.2 a brief look at data types for behavioral modeling
5.3 boolean-equation-based behavioral models of combinational logic
5.4 propagation delay and continuous assignments
5.5 latches and level-sensitive circuits in verilog
5.6 cyclic behavioral models of flip-flops and latches
5.7 cyclic behavior and edge detection
5.8 a comparision of styles for behavioral modeling
5.8.1 continuous-assignment models
5.8.2 dataflow/rtl models
5.8.3 algorithm-based models
5.8.4 port names:a matter of style
5.8.5 simulation with behavioral models
5.9 behavioral models of multiplexers,encoders,and decoders
5.10 dataflow models of a linear-feedback shift register
5.11 modeling digital machines with repetitive algorithms
5.11.1 intellectual property reuse and parameterized models
5.11.2 clock generators
5.12 machines with multicycle operations
5.13 design documentation with functions and tasks:legacy or lunacy?
5.13.1 tasks
5.13.2 functions
5.14 algorithmic state machine charts for behavioral modeling
5.15 asmd charts
5.16 behavioral models of counters,shift registers,and register files
5.16.1 counters
5.16.2 shift registers
5.16.3 register files and arrays of registers(memories)
5.17 switch debounce,metastability,and synchronizers for asynchronous signals
5.18 design example:keypad scanner and encoder
references
problems

6 synthesis of combinational and sequential logic

6.1 introduction to synthesis
6.1.1 logic synthesis
6.1.2 rtl synthesis
6.1.3 high-level synthesis
6.2 synthesis of combinational logic
6.2.1 synthesis of priority structures
6.2.2 exploiting logical don't-care conditions
6.2.3 asic cells and resource sharing
6.3 synthesis of sequential logic with latches
6.3.1 accidental synthesis of latches
6.3.2 intentional synthesis of latches
6.4 synthesis of three-state devices and bus interfaces
6.5 synthesis of sequential logic with flip-flops
6.6 synthesis of explicit state machines
6.6.1 synthesis of a bcd-to-excess-3 code converter
6.6.2 synthesis of a mealy-type nrz-to-manchester line code converter
6.6.3 synthesis of a moore-type nrz-to-manchester line code converter
6.6.4 synthesis of a sequence recognizer
6.7 registered logic
6.8 state encoding
6.9 synthesis of implicit state machines,registers,and counters
6.9.1 implicit state machines
6.9.2 synthesis of counters
6.9.3 synthesis of registers
6.10 resets
6.11 synthesis of gated clocks and clock enables
6.12 anticipating the results of synthesis
6.12.1 synthesis of data types
6.12.2 operator grouping
6.12.3 expression substitution
6.13 synthesis of loops
6.13.1 static loops without embedded timing controls
6.13.2 static loops with embedded timing controls
6.13.3 nonstatic loops without embedded timing controls
6.13.4 nonstatic loops with embedded timing controls
6.13.5 state-machine replacements for unsynthesizable loops
6.14 design traps to avoid
6.15 divide and conquer:partitioning a design
references
problems

7 design and synthesis of datapath controllers

7.1 partitioned sequential machines
7.2 design example:binary counter
7.3 design and synthesis of a risc stored-program machine
7.3.1 risc spm:processor
7.3.2 risc spm:alu
7.3.3 risc spm:controller
7.3.4 risc spm:instruction set
7.3.5 risc spm:controller design
7.3.6 risc spm:program execution
7.4 design example:uart
7.4.1 uart operation
7.4.2 uart transmitter
7.4.3 uart receiver
references
problems

8 programmable logic and storage devices

8.1 programmable logic devices
8.2 storage devices
8.2.1 read-only memory(rom)
8.2.2 programmable rom(prom)
8.2.3 erasable roms
8.2.4 rom-based implementation of combinational logic
8.2.5 verilog system tasks for roms
8.2.6 comparison of roms
8.2.7 rom-based state machines
8.2.8 flash memory
8.2.9 static random access memory
8.2.10 ferroelectric nonvolatile memory
8.3 programmable logic array(pla)
8.3.1 pla minimization
8.3.2 pla modeling
8.4 programmable array logic(pal)
8.5 programmablility of plds
8.6 complex plds(cplds)
8.7 altera max 7000 cpld
8.7.1 shareable expander
8.7.2 parallel expander
8.7.3 i/o control block
8.7.4 timing considerations
8.7.5 device resources
8.7.6 other altera device families
8.8 xilinx xc9500 cplds
8.9 field-programmable gate arrays
8.9.1 the role of fpgas in the asic market
8.9.2 fpga technologies
8.10 altera flex 8000 fpgas
8.11 altera flex 10 fpgas
8.12 altera flex fpgas
8.13 altera chip programmability
8.14 silinx xc4000 series fpga
8.14.1 basic architecture
8.14.2 xc4000 configurable logic block
8.14.3 dedicated fast carry and borrow logic
8.14.4 distributed ram
8.14.5 xc4000 interconnect resources
8.14.6 xc4000 i/o block (iob)
8.14.7 enhancements in the xc4000e and xc4000x series
8.14.8 enhancements in the spartan series
8.15 xilinx spartan xl fpgas
8.16 xilinx spartan ii fpgas
8.17 xilinx virtex fpgas
8.18 embeddable and programmable ip cores for a system on a chip(soc)
8.19 verilog-based design flows for fpgas
8.20 synthesis with fpgas
references
related web sites
problems

9 algorithms and architectures for digital processors

9.1 algorithms,nested-loop programs,and data flow graphs
9.2 design example:halftone pixel image converter
9.2.1 baseline design for a halftone pixel image converter
9.2.2 nlp-based architectures for the halftone pixel image converter
9.2.3 concurrent asmd-based architecture for a halftone pixel image converter
9.2.4 halftone pixel image converter:design tradeoffs
9.2.5 architectures for dataflow graphs with feedback
9.3 digital filters and signal processors
9.3.1 finite-duration impulse response
9.3.2 digital filter design process
9.3.3 infinite-duration impulse response (iir)filter
9.4 building blocks for signal processors
9.4.1 integrators(accumulators)
9.4.2 differentiators
9.4.3 decimation and interpolation filters
9.5 pipelined architectures
9.5.1 design example:pipelined adder
9.5.2 design example:pipelined fir filter
9.6 circular buffers
9.7 fifos and synchronization across clock domains
references
problems

10 architectures for arithmetic processors

10.1 number representation
10.1.1 signed magnitude representation of negative integers
10.1.2 ones complement representation of negative integers
10.1.3 twos complement representation of positive and negative integers
10.1.4 representation of fractions
10.2 functional units for addition and subtraction
10.2.1 ripple-carry adder
10.2.2 carry look-ahead adder
10.2.3 overflow and underflow
10.3 functional units for multiplication
10.3.1 combinational(parallel)binary multiplier
10.3.2 sequential binary multiplier
10.3.3 sequential multiplier design:hierarchical decomposition
10.3.4 stg-based controller design
10.3.5 efficient stg-based sequential binary multiplier
10.3.6 asmd-based sequential binary multiplier
10.3.7 efficient asm-based sequential multiplier
10.3.8 summary of asmd-based sequential multiplier
10.3.9 reduced-register sequential multiplier
10.3.10 implicit-state-machine binary multiplier
10.3.11 booth's-algorithm sequential multiplier
10.3.12 bit-pair encoding
10.4 multiplication of signed binary numbers
10.4.1 product of signed numbers:negative multiplicand,positive multiplier
10.4.2 product of signed numbers:positive multiplicand,negative multiplier
10.4.3 product of signed numbers:negative multiplicand,negative multiplier
10.5 multiplicand of fractions
10.5.1 signed fractions:positive multiplicand,positive multiplier
10.5.2 signed fractions:negative multiplicand,positive multiplier
10.5.3 signed fractions:positive multiplicand,negative multiplier
10.5.4 signed fractions:negative multiplicand,negative multiplier
10.6 functional units for division
10.6.1 division of unsigned binary numbers
10.6.2 efficient division of unsigned binary numbers
10.6.3 reduced-register sequential divider
10.6.4 division of signed(2s complement)binary numbers
references
problems

11 postsynthesis design tasks

11.1 postsynthesis design validation
11.2 postsynthesis timing verification
11.2.1 static timing analysis
11.2.2 timing specifications
11.2.3 factors that affect timing
11.3 elimination of asic timing violations
11.4 false paths
11.5 dynamically sensitized paths
11.6 system tasks for timing verification
11.6.1 timing check:setup condition
11.6.2 timing check:hold condition
11.6.3 timing check:setup and hold conditions
11.6.4 timing check:pulsewidth constraint
11.6.5 timing constraint:signal skew constraint
11.6.6 timing check:clock period
11.6.7 timing check:recovery time
11.7 fault simulation and testing
11.7.1 circuit defects and faults
11.7.2 fault detection and testing
11.7.3 d-notation
11.7.4 automatic test-pattern generation for combinational circuits
11.7.5 fault coverage and defect levels
11.7.6 test generation for sequential circuits
11.8 fault simulation
11.8.1 fault collapsing
11.8.2 serial fault simulation
11.8.3 parallel fault simulation
11.8.4 concurrent fault simulation
11.8.5 probabilistic fault simulation
11.9 fault simulation with verifault-xl
11.9.1 tasks for fault simulation
11.9.2 fault collapsing and classification with verifault-xl
11.9.3 structural and behavioral fault propagation
11.9.4 testbench for fault simulation with verifault-xl
11.9.5 fault descriptors
11.10 jtag ports and design for testability
11.10.1 boundary scan and jtag ports
11.10.2 jtag modes of operation
11.10.3 jtag registers
11.10.4 jtag instructions
11.10.5 tap architecture
11.10.6 tap controller state machine
11.10.7 design example:testing with jtag
11.10.8 design example:built-in self-test
references
problems

a verilog primitives

a.1 multiinput combinational logic gates
a.2 multioutput combinational gates
a.3 three-state gates
a.4 mos transistor switches
a.5 mos pull-up/pull-down
a.6 mos bidirectional switches

b verilog keywords

c verilog data types

c.1 nets
c.2 register variables
c.3 constants
c.4referencing arrays of nets or regs

d verilog operators

d.1 arithmetic operators
d.2 bitwise operators
d.3 reduction operators
d.4 logical operators
d.5 relational operators
d.6 shift operators
d.7 conditional operator
d.8 concatenation operator
d.9 expressions and operands
d.10 operator precedence

e backus-naur formal syntax notation

f verilog language formal syntax

f.1 source text
f.2 declarations
f.3 primitive instances
f.4 module instantiation
f.5 udp declaration and instantiation
f.6 behavioral statements
f.7 specify section
f.8 expressions
f.9 general

g additional features of verilog

g.1 arrays of primitives
g.2 arrays of modules
g.3 hierarchical dereferencing
g.4 parameter substitution
g.5 procedural continuous assignment
g.6 intra-assignment delay
g.7 indeterminate assignment and race conditions
g.8 wait statement
g.9 fork…join statement
g.10 named (abstract)events
g.11 constructs supported by synthesis tools

h flip-flop and latch types

i verilog-2001

i.1 ansi c style changes
i.2 code management
i.3 support for logic modeling
i.4 support for arithmetic
i.5 sensitivity list for event control
i.6 sensitivity list for combinational logic
i.7 parameters
i.8 instance generation

j programming language interface

k websites

l web-based tutorials

list of tables

index

index of verilog modules and user-defined primitives

summary of key verilog features (ieee 1364)