| 《3维超大规模集成电路:2.5维集成方案(英文版)》：3-Dimensional VLSI A 2.5-Dimensional Integration Scheme elaborates theconcept and importance of 3-Dimensional （3-D） VLSI. The authors havedeveloped a new 3-D IC integration paradigm, so-called 2.5-D integration,to address many problems that are hard to resolve using traditional non-monolithic integration schemes. The book also introduces major 3-D VLSIdesign issues that need to be solved by IC designers and Electronic DesignAutomation （EDA） developers. By treating 3-D integration in an integratedframework, the book provides important insights for semiconductorprocess engineers, IC designers, and those working in EDA R&D. |
| Dr. Yangdong Deng is an associate professor at the Institute of Microelectronics, Tsinghua University, China. Dr. Wojciech P. Maly is the U. A. and Helen Whitaker Professor at the Department of Electrical and Computer Engineering, Carnegie Mellon University, USA. |
| list of figures and tables introduction 1.1 2.5-d integration 1.2 enabling technologies 1.2.1 fabrication technology 1.2.2 testing methodology and fault tolerance technique 1.2.3 design technology 1.3 objectives and book organization references a cost comparison of vlsi integration schemes 2.1 non-monolithic integration schemes 2.1.1 multiple-reticle wafer 2.1.2 multiple chip module (mcm) 2.1.3 three-dimensional (3-d) integration 2.2 yield analysis of different vlsi integration approaches 2.2.1 monolithic soc 2.2.2 multiple-reticle wafer (mrw) 2.2.3 three-dimensional (3-d) integration 2.2.4 2.5-d system integration 2.2.5 multi-chip module 2.2.6 summing up 2.3 observations references 3 design case studies 3.1 crossbar 3.2 a 2.5-d rambus dram architecture 3.2.1 tackle the long bus wire 3.2.2 serialized channel in the 3rd dimension 3.3 a2.5-d redesign of piperench 3.3.1 the 2.5-d implementation 3.3.2 simulation results 3.4 a2.5-d integrated microprocessor system 3.4.1 a 2.5-d integrated microprocessor system 3.4.2 an analytical performance model 3.4.3 detailed performance simulation for reduced memory latency 3.5 observations references 4 an automatic 2.5-d layout design flow 4.1 a 2.5-d layout design framework 4.1.1 2.5-d floorplanning 4.1.2 2.5-d placement 4.1.3 2.5-d global routing 4.2 'observations references fioorplanning for 2.5-d integration 5.1 floorplan level evaluation--category 2 circuits 5.1.1 technique 5.1.2 results 5.2 floorplan level evaluation--category 3 circuits 5.2.1 technique 5.2.2 results 5.3 thermal driven floorplanning 5.3.1 chip level thermal modeling and analysis for 2.5-d floorplanning 5.3.2 coupled temperature and leakage estimation 5.3.3 2.5-d thermal driven floorplanning techniques 5.3.4 experimental results 5.4 observations references placement for 2.5-d integration 6.1 pure standard cell designs 6.1.1 placement techniques 6.1.2 benchmarks and layout model 6.1.3 evaluation of vertical partitioning strategies 6.1.4 wire length scaling 6.1.5 wire length reduction 6.1.6 wire length vs. inter-chip contact pitch 6.2 mixed macro and standard cell designs 6.2.1 placement techniques 6.2.2 results and analysis 6.3 observatiohs references a road map of 2.5-d integration 7.1 stacked memory 7.2 dram integration for bandwidth-demanding applications 7.3 hybrid system integration 7.4 extremely high performance systems 7.4.1 highly integrated image sensor system 7.4.2 radar-in-cubc references conclusion and future work 8.1 main contributions and conclusions 8.2 future work 8.2.1 fabrication technology for 2.5-d systems 8.2.2 testing techniques for 2.5-d integration 8.2.3 design technology for 2.5-d integration references index |
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