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| 《Verilog HDL高级数字设计(第2版)(英文版)》特色·重点讨论现代数字电路系统的设计方法·阐述并推广基于Verilog 2001和2005，且可综合的RTL描述和算法建模的设计风格·明确指出了可综合和不可综合循环的区别·讲述了如何应用ASM和ASMD图进行行为级建模·深入讨论基于Verilog 2001和2005的数字处理系统、RISC计算机和各种数据通道控制器、异步和同步FIFO设计的算法和架构及综合的设计实例·给出了150多个经过完全验证的实例，对时序分析、故障模拟、测试和可测性设计进行切合实际的讨论·含有利用Vetilog 2001和2005编写的具备JTAG和BIST可测功能的实用设计案例·每章后均设计了一些涉及面广且难度高的习题·包含一套与《Verilog HDL高级数字设计(第2版)(英文版)》内容配套的可适合实验室实验验证的FPGA设计实例，如ALU、可编程电子锁、有FPFO的键盘扫描器、可纠错的串行通信接口、基于SRAM的控制器、异步和同步FIFO设计、存储器及RISC CPU《Verilog HDL高级数字设计(第2版)(英文版)》支持网站内容包括：所有模型的源文件、仿真实例的测试平台源文件、幻灯片文件、某些工具软件的速成教案及常见问题解答（FAQ） |
| Michael D.Ciletti，科罗拉多大学电气与计算机工程系教授。研究方向包括通过硬件描述语言进行数字系统的建模、综合与验证、系统级设计语言和FPGA嵌入式系统。其著作还有Digital Design，Fourth Edition(其翻译版和影印版均由电子工业出版社出版)。作者曾在惠普、福特微电子和Prisma等公司进行VLSI电路设计的研发工作，在数字系统和嵌入式系统研究、设计等领域有丰富的研发和教学经历。 |
| 1 introduction to digital design methodology 1.1 design methodology—an introduction 1.2 ic technology options 1.3 overview references 2 review of combinational logic design 2.1 combinational logic and boolean algebra 2.2 theorems for boolean algebraic minimization 2.3 representation of combinational logic 2.4 simplification of boolean expressions 2.5 glitches and hazards 2.6 building blocks for logic design references problems 3 fundamentals of sequential logic design 3.1 storage elements 3.2 flip-flops 3.3 busses and three-state devices 3.4 design of sequential machines 3.5 state-transition graphs 3.6 design example: bcd to excess-3 code converter 3.7 serial-line code converter for data transmission 3.8 state reduction and equivalent states references problems 4 introduction to logic design with verilog 4.1 structural models of combinational logic 4.2 logic system, design verification, and test methodology 4.3 propagation delay 4.4 truth table models of combinational and sequential logic with verilog references problems 5 logic design with behavioral models of combinational and sequential logic 5.1 behavioral modeling 5.2 a brief look at data types for behavioral modeling 5.3 boolean equation-based behavioral models of combinational logic 5.4 propagation delay and continuous assignments 5.5 latches and level-sensitive circuits in verilog 5.6 cyclic behavioral models of flip-flops and latches 5.7 cyclic behavior and edge detection 5.8 a comparison of styles for behavioral modeling 5.9 behavioral models of multiplexers, encoders, and decoders 5.10 dataflow models of a linear-feedback shift register 5.11 modeling digital machines with repetitive algorithms 5.12 machines with multicycle operations 5.13 design documentation with functions and tasks: legacy or lunacy? 5.14 algorithmic state machine charts for behavioral modeling 5.15 asmd charts 5.16 behavioral models of counters, shift registers, and register files 5.17 switch debounce, metastability, and synchronizers for asynchronous signals 5.18 design example: keypad scanner and encoder references problems 6 synthesis of combinational and sequential logic 7 design and synthesis of datapath controllers 8 programmable logic and storage devices 9 algorithms and architectures for digital processors 10 architectures for arithmetic processors 11 postsynthesis design tasks a verilog primitives b verilog keywords c verilog data types d verilog operators e verilog language formal syntax f verilog language formal syntax g additional features of verilog h flip-flop and latch types i verilog-2001, 2005 j programming language interface k web sites l web-based resources index |
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