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作 者:(美)Joseph A.Fisher, Paolo Faraboschi, Cliff Young 著
出 版 社:机械工业出版社
出版时间:2006 年9月
I S B N:7111197712
| 本书论述清晰。观点精辟、内容丰富。如果您所采用的技术与VLIW或“嵌入式计算”有关,毫无疑问,您有必要读这本书。如果您关注计算机系统设计或程序设计,则您仍有必要读一读这本书,因为它会开阔您的眼界。当然,您不必同意作者的每一个观点,但是您会了解作者努力去说明的内容,而他们的论述和观点将引发您去进行深入的思考。——摘自Robert Colwell为本书所作的序 |
| Joseph A.Fisher 是惠普实验室的高级研究员,从1990年开始在惠普实验室致力于指令级并行、定制嵌入式VLIW处理器及其编译器的研究工作。他曾就读于纽约大学科朗研究院,1997年获得博士学位,在求学期间,他还发明了跟踪调度编译器算法并创造了“指令级并行”这一术语。作为一名耶鲁大学的教授,他创造并命名了VLIW体系结构,同时还发明了指令级并行(ILP)的许多基本技术。他获得的荣誉有:1984年度美国国家科学基金会杰出青年科学家总统奖以及2003年度ACM/IEEE的Eckert-Mauchly奖等。. Paolo Far.. << 查看详细 |
| about the authors foreword. preface content and structure the vex (vliw example) computing system audience cross-cutting topics how to read this book figure acknowledgments acknowledgments chapter 1 an introduction to embedded processing 1.1 what is embedded computing? 1.2 distinguishing between embedded and general-purpose computing 1.3 characterizing embedded computing 1.4 embedded market structure 1.5 further reading 1.6 exercises chapter 2 an overview of vliw and ilp 2.1 semantics and parallelism 2,2 design philosophies .2.3 role of the compiler 2.4 vliw in the embedded and dsp domains 2.5 historical perspective and further reading 2.6 exercises chapter 3 an overview of isa design 3.1 overview: what to hide 3.2 basic vliw design principles 3.3 designing a vliw isa for embedded systems 3.4 instruction-set encoding 3.5 vliw encoding 3.6 encoding and instruction-set extensions 3.7 further reading 3.8 exercises chapter 4 architectural structures in isa design 4.1 the datapath 4.2 registers and clusters 4.3 memory architecture 4.4 branch architecture 4.5 speculation and predication 4.6 system operations 4.7 further reading 4.8 exercises chapter 5 microarchitecture design 5.1 register file design 5.2 pipeline design 5.3 vliw fetch, sequencing, and decoding 5.4 the datapath 5.5 memory architecture 5.6 the control unit 5.7 control registers 5.8 power considerations 5.9 further reading 5.10 exercises chapter 6 system design and simulation 6.1 system-on-a-chip (sec) 6.2 processor cores and sec 6.3 overview of simulation 6.4 simulating a vliw architecture 6.5 system simulation.. 6.8 validation and verification 6.7 further reading 6.8 exercises chapter 7 embedded compiling and toolchains 7.1 what is important in an ilp compiler? 7.2 embedded cross-development toolchains 7.3 structure of an ilp compiler 7.4 code layout 7.5 embedded-specific tradeoffs for compilers 7.6 dsp-specific compiler optimizations 7.7 further reading 7.8 exercises chapter 8 compiling for vl1ws and ilp 8.1 profiling 8.2 scheduling 8.3 register allocation 8.4 speculation and predication 8.5 instruction selection 8.6 further reading 8.7 exercises chapter 9 the run-time system 9.1 exceptions, interrupts, and traps 9.2 application binary interface considerations 9.3 code compression 9.4 embedded operating systems 9.5 multiprocessing and multithreading 9.6 further reading 9.7 exercises chapter 10 application design and customization 10.1 programmiug language choices 10.2 performance, benchmarking, and tuning 10.3 scalability and customizability 10.4 further reading 10.5 exercises chapter 11 application areas 11.1 digital printing and imaging 11.2 telecom applications 11.3 other application areas 11.4 further reading 11.5 exercises appendix a the vex system a.1 the vex instruction-set architecture a.2 the vex run-time architecture a.3 the vex c compiler a.4 visualization tools a.5 the vex simulation system a.6 customizing the vex toolchzin a.7 examples of tool usage a.8 exercises appendix b glossary appendix c bibliography index ... |
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