最 低 价：￥18.75
| FARZAD NEKOOGAR is the author of Digital Control Using Digital Signal Processing and Timing Verification of Application Specific integrated Circuits, both from Prentice Hall PTR. He has over 15 years of experience in design and verification of ASICs (front-end and back-end), SOCs, FPGAs, boards, and systems. He has lectured at the University of California on signal processing, chip design, and theoretical physics. FARANAK NEKOOGAR has many y.. << 查看详细 |
| list of abbreviations preface acknowledgments introduction 1.1 introduction 1.2 voice over ip soc 1.3 intellectual property 1.4 soc design challenges 1.5 design methodology 1.6 summary 1.7 references overview of asics 2.1 introduction 2.2 methodology and design flow 2.3 fpga to asic conversion 2.4 verification 2.5 summary 2.6 references 3 soc design and verification 3.1 introduction .3.2 design for integration 3.3 soc verification 3.4 set-top-box soc 3.5 set-top-box soc example 3.6 summary 3.7 references 4 physical design 4.1 introduction 4.2 overview of physical design flow 4.3 some tips and guidelines for physical design 4.4 modern physical design techniques 4.5 summary 4.6 references low-power design 5.1 introduction 5.2 power dissipation 5.3 low-power design techniques and methodologies 5.4 low-power design tools 5.5 tips and guidelines for low-power design 5.6 summary 5.7 references a low-power design tools powertheater powertheater analyst powertheater designer b open core protocol (ocp) highlights capabilities advantages key features phase-locked loops (plls) pll basics pll ideal behavior pll errors glossary index |
![EDA工程的理论与实践——SOC系统芯片设计[按需印刷]](http://images.china-pub.com/ebook15001-20000/18486/zcover.jpg)
内容加载中，请稍后...
商品评论（0条）