复杂SoC设计（英文影印版）

.1.4 preview: an improved design methodology for soc design
1.4.1 the soc design flow
1.4.2 configurable processor as building block
1.4.3 a trivial example
1.4.4 results of application-specific processor configuration
1.4.5 the processor as soc building block
1.4.6 solving the system design problem
1.4.7 implications of improved soc methodology
1.4.8 the transition to processor-based soc design
1.5 further reading
chapter 2 soc design today
2.1 hardware system structure
2.1.1 how is rtl used today?
2.1.2 control, data path, and memory
2.1.3 hardware trends
2.2 software structure
2.2.1 software trends
2.3 current soc design flow
2.4 the impact of semiconductor economics
2.5 six major issues in soc design
2.5.1 changing market needs
2.5.2 inadequate product volume and longevity
2.5.3 inflexibility in the semiconductor supply chain
2.5.4 inadequate performance, efficiency, and cost
2.5.5 risk, cost, and delay in design and verification
2.5.6 inadequate coordination between hardware and software teams
2.5.7 solving the six problems
2.6 further reading
chapter 3 a new look at soc design
3.1.1 the basics of processor-centric soc architecture
3.1.2 processor generation
3.2 accelerating processors for traditional software tasks
3.2.1 the evolution of generic processors
3.2.2 explaining configurability and extensibility
3.2.3 processor extensibility
3.2.4 designer-defined instruction sets
3.2.5 memory systems and configurability
3.2.6 the origins of configurable processors
3.3 example: tensilica xtensa processors for eembc benchmark
3.3.1 eembc consumer benchmarks
3.3.2 telecommunications
3.3.3 eembc networking benchmarks
3.3.4 the processor as rtl alternative
3.4 system design with multiple processors
3.4.1 available concurrency
3.4.2 parallelism and power
3.4.3 a pragmatic view of multiple processor design methodology
3.4.4 forms of partitioning
3.4.5 processor interface and interconnect
3.4.6 communications between tasks
3.5 new essentials of soc design methodology
3.5.1 soc design flow
3.5.2 the essential phases of the new flow
3.6 addressing the six problems
3.6.1 make the soc more programmable
3.6.2 build an optimized platform to aggregate volume
3.6.3 use portable ip foundations for supply leverage
3.6.4 optimize processors for performance and efficiency
3.6.5 replace hard-wired design with tuned processors
3.6.6 unify hardware and software with processor-centric soc methodology
3.6.7 complex soc and the six problems
3.7 further reading
chapter 4 system-level design of complex socs
4.1 complex soc system architecture opportunities
4.1.1 the basic process of parallel design
4.1.2 the soc as a network of interacting components
4.1.3 impact of silicon scaling on system partitioning
4.1.4 why multiple processors
4.1.5 types of concurrency and system architecture
4.1.6 latency, bandwidth and communications structure
4.1.7 reliability and scalability in soc communications architecture
4.1.8 communications programming flexibility
4.1.9 early vs. late-binding of interaction mechanisms
4.2 major decisions in processor-centric soc organization
4.2.1 the starting point: essential interfaces and computation
4.2.2 parallelizing a task
4.2.3 assigning tasks to processors
4.2.4 choosing the right communications structure
4.3 communication design= software mode + hardware
interconnect
4.3.1 software communication modes
4.3.2 message passing
4.3.3 shared memory
4.3.4 device driver
4.4 hardware interconnect mechanisms
4.4.1 buses
4.4.2 direct connect ports
4.4.3 data queues
4.4.4 time-multiplexed processor
4.5 pefformance-drven communication design
4.5.2 system modeling languages
4.5.3 system modeling example: xtmp
4.5.4 balancing computation and communications
4.6 the soc design flow
4.6.1 recommended design flow
4.6.2 shifts in soc design methodology
4.7 non-processor building blocks in complex soc
4.7.1 memories
4.7.2 i/o peripherals
4.7.3 hardwired logic blocks
4.8 implications of processor-centric soc architecture
4.9 further reading
chapter 5 configurable processors: a software view
5.1 processor hardware/software cogeneration
5.1.1 applications, programming languages, and processor architecture
5.1.2 a quick example: pixel blending
5.2 the process of instruction definition and application tuning
5.2.1 profiling and performance
5.2.2 new instructions for performance and efficiency
5.3 the basics of instruction extension
5.3.1 instruction extension methods
5.3.2 upgrading the application
5.3.3 the tradeoff between instruction-set performance and generality
5.3.4 operation fusion
5.3.5 compound operations
5.3.6 simd instructions
5.4 the programmer's model
5.4.1 the base user instruction set
5.4.2 the application-specific instruction set
5.4.3 the system-programming instruction set
5.5 processor performance factors
5.5.1 the software development environment
5.5.2 the software runtime environment
5.5.3 processor generation flow
5.6 example: tuning a large task
5.7 memory-system tuning
5.7.1 basic memory-system strategy
5.7.2 detailed memory-system tuning
5.7.3 aggregate memory system performance
5.7.4 inner-loop data-reference tuning
5.8 long instruction words
5.8.1 code size and long instructions
5.8.2 long instruction words and automatic processor generation
5.9 fully automatic instruction-set extension
5.10 further reading
chapter 6 configurable processors: a hardware view
6.1 application acceleration: a common problem
6.2 introduction to pipelines and processors
6.2.1 pipelining fundamentals
6.2.2 risc pipeline basics
6.2.3 pipelines for extended instruction-set implementation
6.2.4 guarantee of correctness in processor hardware extension
6.3 hardware blocks to processors
6.3.1 the basic transformation of hardware into instructions
6.3.2 one primitive operation per instruction
6.3.3 multiple independent operations per instruction
6.3.4 pipelined instruction
6.3.5 tradeoffs in mapping hardware functions to processor instructions
6.4 moving from hardwired engines to processors
6.4.1 translating finite-state machines to software
6.4.2 designing application-specific processors for flexibility
6.4.3 moving from microcoded engines to processors
6.4.4 microcode data paths
6.4.5 encoding operations
6.4.6 microprograms
6.5 designing the processor interface
6.5.1 memory-mapped ram
6.5.2 memory-mapped queues and registers
6.5.3 wire-based input and output
6.6 a short example: atm packet segmentation and reassembly
6.7 novel roles for processors in hardware replacement
6.7.1 the deeply buffed task engine
6.7.2 designing with spare processors
6.7.3 the system-monitor processor
6.8 processors, hardware implementation, and verification flow
6.8.1 hardware flow
6.8.2 verification flow
6.9 progress in hardware abstraction
6.10 further reading
chapter 7 advanced topics in soc design
7.1 pipelining for processor performance
7.2 inside processor pipeline stalls
7.2.2 pipelines and exceptions
7.2.3 alternative pipelining for complex instructions
7.3 optimizing processors to match hardware
7.3.1 overcoming differences in branch architecture
7.3.2 overcoming limitations in memory access
7.4 multiple processor debug and trace
7.4.1 mp debug
7.4.2 mp trace
7.5 issues in memory systems
7.5.1 pipelining with multiple memory ports
7.5.2 memory alignment in simd instruction sets
7.5.3 synchronization mechanisms for shared memory
7.5.4 instruction rom
7.6 optimizing power dissipation in extensible processors
7.6.1 core power
7.6.2 impact of extensibility on performance
7.6.3 memory power
7.6.4 cache power dissipation guide
7.7 essentials of tie
7.7.1 tie operations
7.7.2 tie states and register files
7.7.3 external tie ports and queues
7.7.4 tie constants
7.7.5 tie function scheduling (use and del)
7.7.6 using built-in registers, interfaces, and functions with tie
7.7.7 shared and iterative tie functions
7.7.8 multi-slot instructions
7.8 further reading
chapter 8 the future of soc design: the sea of processors
8.1.1 what's happening to soc design?
8.1.2 soc and roi
8.1.3 the designer's dilemma
8.1.4 the limitations of general-purpose processors
8.1.5 the new processor
8.1.6 what makes these processors different?
8.1.7 the soc design transition
8.2 why is software programmability so central?
8.3 looking into the future of soc
8.4 processor scaling model
8.4.1 summary of model assumptions
8.5 future applications of complex socs
8.6 the future of the complex soc design process
8.7 the future of the industry
8.8 the disruptive-technology view
8.9 the long view
8.10 further reading
index