时钟发生器在片上系统处理器中的应用(英文影印版)

. 3.7 summary
4.jitter analysis in phase-locked loops
4.1 introduction
4.2 jitter basics
4.3 jitter in voltage controlled oscillators
4.4 jitter performance of closed-loop pll system
4.5 coupling noise effects on jitter
4.6 summary
5.low-jitter pll architectures
5.1 introduction
5.2 differential pll architecture.
5.3 supply voltage regulated pll architectures
5.4 adaptive pll architectures
5.5 resistorless loop filter plls
5.6 delay-locked loop frequency multipliers
5.7 summary
6.digital pll design
6.1 introduction
6.2 basic topology
6.3 z-domain analysis
6.4 circuit implementation issues
6.5 alternate digital pll for clock generation
6.6 summary
7.dsp clock generator architectures
7.1 introduction
7.2 sampling clock requirements for data converters
7.3 jitter in frequency dividers
7.4 fractional-n plls as clock generators
7.5 oversampled pll topologies
7.6 direct digital synthesis with analog interpolation
7.7 summary
8.design for testability in plls
8.1 introduction
8.2 verification of soc plls
8.3 jitter measurement techniques
8.4 design for testability and self-test in plls
8.5 summary
9.clock partitioning and skew control
9.1 introduction
9.2 clock distribution networks in socs
9.3 performance limitations in clock networks
9.4 active skew management strategies
9.5 multi-phase clock generator
9.6 low-power clock distribution strategies
9.7 multi-clock domain interfacing
9.8 summary
index