现代VLSI电路设计（第二版）（英文影印版）

.3 logic gates
3.1introduction
3.2combinational logic functions
3.3static complementary gates
3.4wires and delay
3.5switch logic
3.6alternative gate circuits
3.7references
3.8problems
4 combinational logic networks
4.1introduction
4.2layout design methods
4.3simulation
4.4combinational network delay
4.5crosstalk
4.6power optimization
4.7switch logic networks
4.8combinational logic testing
4.9references
4.10problems
5 sequential machines
5.1introduction
5.2latches and flip-flops
5.3sequential systems and clocking disciplines
5.4sequential system design
5.5power optimization
5.6design validation
5.7sequential testing
5.8references
5.9problems
6 subsystem design
6.1introduction
6.2subsystem design principles
6.3combinational shifters
6.4adders
6.5alus
6.6multipliers
6.7high-density memory
6.8field-programmable gate arrays
6.9programmable logic arrays
6.10references
6.11problems
7 floorplanning
7.1introduction
7.2floorplanning methods
7.3off-chip connections
7.4references
7.5problems
8 architecture design
8.1introduction
8.2register-transfer design
8.3high-level synthesis
8.4architectures for low power
8.5architecture testing
8.6references
8.7problems
9 chip design
9.1introduction
9.2design methodologies
9.3kitchen timer chip
9.4pdp-8 data path
9.5references
9.6problems
10 cad systems and algorithms
10.1introduction
10.2cad systems
10.3simulation
10.4layout synthesis
10.5layout analysis
10.6timing analysis and optimization
10.7logic synthesis
10.8test generation
10.9sequential machine optimizations
10.10scheduling and binding
10.11hardware/software co-design
10.12references
10.13problems
appendix a:a chip designer's lexicon
appendix b:chip design projects
b.1class project ideas
b.2project proposal and specification
b.3design plan
b.4design checkpoints and documentation
appendix c:design modeling
c.1introduction
c.2hardware modeling in vhdl
c.3hardware modeling in c
references
index