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| The LNCS series reports state-of-the-art results in computer science research,development,and education,at a high level and in both printed and electronic form.Enjoying tight cooperation with the R&D community,with numerous individuals,as well as with prestigious organizations and societies,LNCS has grown into the most comprehensive computer science resarch forum available. The scope of LNCS,including its subseries LNAI,spans the whole range of computer science and information technology including interdisciplinary topics in a variety of application fields.The type of material publised traditionally includes. -proceedings(published in time for the respective conference) -post-proceedings(consisting of thoroughly revised final full papers) -research monographs(which may be basde on outstanding PhD work,research projects,technical reports,etc.) |
| Keynote Address I Processor Architecture for Trustworthy Computers Session 1A: Energy Efficient and Power Aware Techniques Efficient Voltage Scheduling and Energy-Aware Co-synthesis for Real-Time Embedded Systems Energy-Effective Instruction Fetch Unit for Wide Issue Processors Rule-Based Power-Balanced VLIW Instruction Scheduling withUncertainty An Innovative Instruction Cache for Embedded Processors Dynamic Voltage Scaling for Power Aware Fast Fourier Transform (FFT) Processor David Fitrio, Jugdutt (Jack) Singh, Aleksandar (Alex) Stojcevski Session 1B" Methodologies and Architectures for Application-Specific Systems Design of an Efficient Multiplier-Less Architecture for Multi-dimensional Convolution A Pipelined Hardware Architecture for Motion Estimation of H.264/AVC Embedded Intelligent Imaging On-Board Small Satellites Architectural Enhancements for Color Image and Video Processing on Embedded Systems A Portable Doppler Device Based on a DSP with High- Performance Spectral Estimation and Output Session 2A: Processor Architectures and Microarchitectures A Power-Efficient Processor Core for Reactive Embedded Applications A Stream Architecture Supporting Multiple Stream Execution Models The Challenges of Massive On-Chip Concurrency FMRPU: Design of Fine-Grain Multi-context Reconfigurable Processing Unit Session 2B: High-Reliability and Fault-Tolerant Architectures Modularized Redundant Parallel Virtual File System Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures A Fault-Tolerant Routing Strategy for Fibonacci-Class Cubes Embedding of Cycles in the Faulty Hypercube Session 3A: Compier and OS for Emerging Architectures …… Keynote Address II Author Index |
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