最 低 价：￥53.60
定 价：￥68.00
作 者：（美）马诺（Mano,M.M.），（美）西勒提（Ciletti,M.D.）著 著
出 版 社：电子工业出版社
出版时间：2008-7-1
I S B N：9787121068959
| 新特性：保留了前一版中经检验的经典内容，根据IEEE标准1364-2001及1364-2005，为确保所有的示例符合数字硬件建模的实践要求，更新和扩充了有关Verilog HDL的内容，适用于初学者和中高级读者，例题与习题丰富，并在书末给出了部分习题的答案，教辅支持材料齐全。 |
| 1.Digital Systems and Binary Numbers. 1.1 Digital Systems 1.2 Binary Numbers 1.3 Number-Base Conversions 1.4 Octal and Hexadecimal Numbers 1.5 Complements 1.6 Signed Binary Numbers 1.7 Binary Codes 1.8 Binary Storage and Registers 1.9 Binary Logic 2 Boolean Algebra and Logic Gates 2.1 Introductiontlon 2.2 Basic Definitions 2.3 Axiomatic Definition of Boolean Algebra 2.4 Basic Theorems and Properties of Boolean Alqebra 2.5 Boolean Functions 2.6 Canonical and Standard Forms 2.7 0ther LogiC 0perations 2.8 DiqitaI Loqic Gates 2.9 Inteqrated Circuits 3.Gate-Level Minimization 3.1 Introduction 3.2 The Map Method 3.3 Four.Variable Map 3.4 Five.Variable Map 3.5 Product..0f..Sums Simplification 3.6 Don’t-Care Conditions 3.7 NAND and NOR Implementation 3.8 Other Tw0—Level Implementations 3.9 Exclusive.OR Function 3.10 Hardware Description Language 4.Combinational Logical 4.1 Introduction 4.2 Combinational Circuits 4.3 Analysis Procedure 4.4 Design Procedure 4.5 Binary Adder.Subtractor 4.6 Decimal Adder 4.7 Binary Multiplier 4.8 Maqnitude Comparator 4.9 Decoders 4.10 Encoders 4.11 Multiplexers 4.12 HDL Models of Combinational Circuits 5.Synchronous Sequential Logic 5.1 IntrOduction 5.2 Sequential Circuits 5.3 Storage Elements：Latches 5.4 Storage Elements：Flip·Flops 5.5 Analysis of Clocked Sequential Circuits 5.6 Synthesizable HDL Models of SequentiaCircuits 5.7 State Reduction and Assignment 5.8 Design Procedure 6.Registers and Counters 6.1 Registers 6.2 Shift Registers …… 7.Memory and Programmable Logic 8.Design at the Register Transfer Level 9.Asynchronous Sequential Logic 10.Digital Integrated Circuits 11.Laboratory Experiments with Standard ICs and FPGAs 12.Standard Graphic Symbols 13.Answers to Selected Problems Index |
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